Semiconductor memory device having a redundancy area
US8614925B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2010 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.