Vertical transistor with hardening implatation

US8617952B2 · kind B2 · utility

Assignee

• Seagate Technology LLC · US

Inventors

• Young-Pil Kim · Eden Prairie, US
• Hyung Kew Lee · Gunpo-si, KR
• Peter Nicholas Manos · Boise, US
• Chulmin Jung · Boise, US
• Maroun Georges Khoury · Burnsville, US
• Dadi Setiadi · Edina, US

Key dates

• Filing date: Sep 28, 2010
• Grant date: Dec 31, 2013
• Expiry date: May 31, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/253

Abstract

A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.