Flange package for a semiconductor device
US8618650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Nov 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.