Delay circuit and associated method
US8618857B2 · kind B2 · utility
2Cited by
21References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | May 8, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.