Generating high-frequency, non-overlapping clocks
US8618859B1 · kind B1 · utility
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1References
21Claims
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Key dates
| Filing date | Nov 1, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Nov 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for generation of high frequency, non-overlapping clocks may include receiving input clock signals at a clock input node of a circuit. Multiple feedback signals may be received at a number of input feedback nodes of the circuit. At a startup node, a startup signal of the circuit may be received, and, in response to receiving the startup signal, an output clock may be generated at a predefined portion of at least one of the received input clock signals. A stable high frequency output clock may be generated at an output stage by utilizing the feedback signals received by the input feedback nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.