Static random-access memory having read circuitry with capacitive storage
US8619464B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Nov 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.