Two-port SRAM write tracking scheme
US8619477B2 · kind B2 · utility
5Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | May 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.