Semiconductor memory device incorporating an interface chip for selectively refreshing memory cells in core chips
US8619486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2011 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.