Multi-stage interference suppression
US8619928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2009 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Feb 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03726
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-stage interference suppression receiver includes a short equalizer section configured to operate on a first portion of a received signal received over a channel to produce a first equalized signal and a first estimate of the channel, a channel estimator section configured to operate on the first equalized signal to produce a second equalized signal, the channel estimator section comprising a linear estimator and a non-linear estimator, a long equalizer section configured to operate on a second portion of the received signal to produce a first estimate of symbols in the received signal and a second estimate of the channel and an interference canceller section configured to operate on the first estimate of symbols in the received signal to generate a second estimate of symbols in the received signal based on, at least in part, the second estimate of the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.