Multi-purpose phase-locked loop for low cost transceiver
US8619931B1 · kind B1 · utility
4Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2009 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/002
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.