Virtualizing processor memory protection with “L1 iterate and L2 swizzle”
US8621136B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for providing shadow page tables that virtualize processor memory protection. In one embodiment, two shadow L2 page tables are maintained for each section, for example, each 1 MB section, of guest address space covered by a shadow L1 descriptor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.