Flash memory apparatus for controlling operation in response to generation of interrupt signal and method of controlling the same
US8621140B2 · kind B2 · utility
3Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.