Controlling access to a cache memory using privilege level information
US8621149B2 · kind B2 · utility
5Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jul 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.