Obfuscated hardware multi-threading
US8621186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2011 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/755
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Obfuscating a multi-threaded computer program is carried out using an instruction pipeline in a computer processor by streaming first instructions of a first thread of a multi-threaded computer application program into the pipeline, the first instructions entering the pipeline at the fetch stage, detecting a stall signal indicative of a stall condition in the pipeline, and responsively to the stall signal injecting second instructions of a second thread of the multi-threaded computer application program into the pipeline. The injected second instructions enter the pipeline at an injection stage that is disposed downstream from the fetch stage up to and including the register stage for processing therein. The stall condition exists at one of the stages that is located upstream from the injection stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.