Optimized Viterbi decoder and GNSS receiver
US8621335B2 · kind B2 · utility
1Cited by
10References
36Claims
0Family size
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Key dates
| Filing date | Oct 27, 2008 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Aug 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6583
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realized for embedding Viterbi acceleration logic efficiently into a GNSS chipset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.