Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
US8621399B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 27, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.