Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set
US8621410B2 · kind B2 · utility
3Cited by
25References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Mar 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG16Z99/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.