Micro-regions for auto place and route optimization
US8621412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Sep 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.