Mixed linear/square-root encoded single slope ramp provides a fast, low noise analog to digital converter with very high linearity for focal plane arrays
US8624769B2 · kind B2 · utility
5Cited by
10References
18Claims
0Family size
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Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.