Method and system for non stalling pipeline instruction fetching from memory
US8624906B2 · kind B2 · utility
2Cited by
153References
14Claims
0Family size
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Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Sep 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for graphics instruction fetching. The method includes executing a plurality of threads in a multithreaded execution environment. A respective plurality of instructions are fetched to support the execution of the threads. During runtime, at least one instruction is prefetched for one of the threads to a prefetch buffer. The at least one instruction is accessed from the prefetch buffer if required by the one thread and discarded if not required by the one thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.