Potential relationship in an erasing operation of a nonvolatile semiconductor memory
US8625349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2009 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Sep 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.