Memory devices and program methods thereof
US8625367B2 · kind B2 · utility
10Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jun 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.