Method and system of testing bit error rate using signal with mixture of scrambled and unscrambled bits
US8627156B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Apr 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/244
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device under test (DUT) is tested by: receiving a signal transmitted by the DUT, wherein the signal includes first portions that include scrambled bits produced from a selected bit pattern and a selected scrambling algorithm, and further includes second portions that include unscrambled bits, the first portions and second portions being interspersed within the signal; detecting received scrambled bits within the received signal; generating a test bit sequence using the selected scrambling algorithm and the selected bit pattern, including generating a bit of the test bit sequence for each of the received scrambled bits within the received signal, and not generating a bit of the test bit sequence for each of the received unscrambled bits within the received signal; and comparing the received scrambled bits to the test bit sequence to determine a bit error rate of the received signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.