Decoding device and decoding method
US8627168B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Oct 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1137
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multistage difference cyclic permutation unit (106) for performing multistage cyclic permutation, an address administration unit (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement unit (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control unit (110) for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control unit (110) generates a reading start address in the next decoding of the column block and stores it into the address administration unit (104). In this manner, a device configuration capable of reducing a device size of a decoding device for pseudo-cyclic LDPC codes composed of cyclic permutation matrix blocks with a fixed degree of parallelism and an arbitrary cyclic permutation size is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.