Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
US8627188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Dec 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.