Systems and methods for fixing pin mismatch in layout migration
US8627247B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jul 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.