Multi-level parallelism of process execution in a mutual exclusion domain of a processing system
US8627331B1 · kind B1 · utility
16Cited by
63References
36Claims
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Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Sep 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique is described for improving throughput in a processing system, such as a network storage server. The technique provides multiple levels (e.g., a hierarchy) of parallelism of process execution within a single mutual exclusion domain, in a manner which allows certain operations on metadata to be parallelized as well as certain operations on user data. The specific parallelization scheme used in any given embodiment is based at least partly on the underlying metadata structures used by the processing system. Consequently, a high degree of parallelization possible, which improves the throughput of the processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.