Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

US8629022B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dureseti Chidambarrao · Weston, US
• Sunfei Fang · Lagrangeville, US
• Yue Liang · San Jose, US
• Xiaojun Yu · Fishers, US
• Jun Yuan · San Diego, US

Key dates

• Filing date: Mar 15, 2012
• Grant date: Jan 14, 2014
• Expiry date: Mar 15, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83135

Abstract

A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.