Thin film transistor array panel and method for manufacturing the same
US8629861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2013 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | May 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6729
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the drain electrode, forming a negative photosensitive organic layer on the passivation layer, heat treating the negative photosensitive organic layer to form an insulating layer including a first portion, and a second portion that is thinner than the first portion, and forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer. The pixel electrode is disposed on the first portion, the first and second contact assistants are disposed on the second portion, and the thickness of the second portion is less than about 1.5 micrometers (μm).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.