Self-disabling chip enable input
US8630107B2 · kind B2 · utility
2Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Aug 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06562
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.