Memory devices and methods for high random transaction rate
US8630111B2 · kind B2 · utility
1Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Apr 9, 2013 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Apr 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.