Nonvolatile memory devices having memory cell arrays with unequal-sized memory cells and methods of operating same
US8630124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2011 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Jan 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Nonvolatile memory devices include a two-dimensional array of nonvolatile memory cells having a plurality of memory cells of unequal size therein. These memory cells may include those that have unequal channel widths associated with respective word lines and those having unequal channel lengths associated with respective bit lines that are connected to corresponding strings of nonvolatile memory cells (e.g., NAND-type strings). Control circuitry is also provided that is electrically coupled to the two-dimensional array of nonvolatile memory cells. This control circuitry may operate to concurrently program first and second nonvolatile memory cells having unequal sizes from an erased state (e.g., logic 1) to an equivalent programmed state (e.g., logic 0). This is done by establishing unequal first and second word line-to-channel region voltages in the first and second nonvolatile memory cells, respectively, during an operation to program a row of memory cells in the two-dimensional array of nonvolatile memory cells, which includes the first and second nonvolatile memory cells of unequal size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.