Multiple-port memory device comprising single-port memory device with supporting control circuitry
US8630143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2013 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.