Interconnection method and device, for example for systems-on-chip
US8631184B2 · kind B2 · utility
4Cited by
7References
18Claims
0Family size
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Key dates
| Filing date | May 20, 2011 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.