Cache memory power reduction techniques
US8631207B2 · kind B2 · utility
3Cited by
25References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2009 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Dec 26, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.