Via selection in integrated circuit design
US8631375B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Apr 10, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.