Low power slope-based analog-to-digital converter
US8633845B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2012 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Apr 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.