System for video frame synchronization using sub-frame memories
US8634023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Nov 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0105
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method of using the circuit for video frame synchronization are provided. The circuit includes a memory having a capacity less than a full video frame and a “first in first out” (FIFO) interface controlling the memory, further removing the post-read buffer in the memory, and overwriting the post-read buffer in the memory with new data. Some embodiments of the circuit for video frame synchronization provide a wide data bus having a high bandwidth interface to the memory circuit to allow reduced memory clock rate. Some embodiments of the circuit further include a processor that produces a clock signal and measures an input data rate. The processor controls the FIFO interface to generate an output data stream at a preselected frequency, with a preselected phase. More generally, other embodiments of the present invention provide a circuit wherein the processor may be used as a data rate converter and video input timing aberration filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.