Carryless multiplication preformatting apparatus and method
US8635262B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2010 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | May 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.