Memory system and method for passing configuration commands
US8635418B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.