Trouble analysis apparatus
US8635496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2009 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Jul 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0706
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements. The trouble source detection portion determines whether or not directions from the selected error functional element to other error functional elements conform to the spreading directions included in the system topology inf…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.