Method for manufacturing graphene nano array and field-effect transistor including the same
US8637346B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Dec 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/20
- WIPO fieldMaterials, metallurgy
- WIPO sectorChemistry
Abstract
The present disclosure provides a method for manufacturing a graphene nano array. The method includes: preparing a substrate having a graphene sheet disposed thereon; sequentially forming a protective layer, a sacrificial layer and a resist layer on the graphene sheet; forming a hole pattern in a surface of the resist layer; etching the sacrificial layer and the protective layer along the hole pattern to form a trench such that a portion of the protective layer adjacent to the graphene sheet can remain; forming a metal layer of a nanocup pattern along a sidewall of the trench while rotating the trench; removing a lower surface of the metal layer to form a metal layer in a nanotube pattern; removing the resist layer and the sacrificial layer; etching the protective layer and the graphene sheet adjacent to the protective layer along the nanotube pattern; and removing the protective layer and the metal layer, thereby providing a graphene nano array having a large area at low cost. The graphene nano array may be used as channels of a field-effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.