High voltage durability transistor and method for fabricating same
US8637385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2007 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Sep 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.