Semiconductor devices including vertical channel pattern
US8637917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2011 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.