Laminated chip electronic component, board for mounting the same, and packing unit thereof
US8638543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10015
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.