Multi-bit resistance measurement
US8638598B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Oct 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example embodiment is a method for determining a binary value of a memory cell represented by an electrical resistance level of the memory cell. The method includes iteratively charging shunt capacitors having different capacitances until a selected shunt capacitor causes the voltage to decay through the memory cell to a reference voltage within a predetermined time range. A binary value of the most significant bits of the memory cell is determined based on the selected shunt capacitor. The selected shunt capacitor is then charged to a second voltage and the binary value of the least significant bits of the memory cell is determined based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.