Jitter digitizer
US8639461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2009 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit and method for digitizing jitter in a high speed digital signal receives a digital signal using a comparator and supplies a clock signal to a counter. The circuit and method determine the frequency of the digital signal using the clock signal and the counter, and calculate the period of the digital signal based on the frequency (using a logic element). The method and circuit provide a linearized delay for jitter analysis based on the period of the digital signal (using a delay shift circuit) and output a delayed digital signal from the digital signal based on the linearized delay (using a measure delay circuit). The circuit and method supply the digital signal and the delayed digital signal to a programmable unit. The programmable unit comprises flip flops. The circuit and method count transitions of the flip flops within the programmable unit using the counter. The flip flops transition when the digital signal differs from the delayed digital signal. The circuit and method repeat the counting of the transitions of the flip flops for different time intervals to generate a jitter histogram of the digital signal using the logic element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.