Method and system for facilitating communication between a host and downstream devices in a data storage system
US8639864B1 · kind B1 · utility
1Cited by
14References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Nov 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A diplex FPGA is utilized to fan out a single high speed host universal asynchronous receiver transmitter (“UART”) channel into a number of diplex UART channels. The diplex FPGA includes a microprocessor, memory, a host UART and a number of diplex UARTs. In operation, the microprocessor polls each of the UARTs in a “round robin” manner and accepts packets from the host UART for transmission downstream and from the diplex UARTs for transmission upstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.