Reducing write amplification in a cache with flash memory used as a write cache
US8639883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jan 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.