Address-based hazard resolution for managing read/write operations in a memory cache
US8639889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2011 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Nov 27, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.